Constructive Timing Violation for Improving Energy E ciency

A novel technique to improve energy e ciency is disclosed. It relies on a fault-tolerance mechanism for timing constraints based on speculative execution technique. Since power reduces quadratically with supply voltage, supply voltage reduction can result in substantial power savings. However, it also causes larger gate delay, and thus clock must be slow down in order not to violate timing constraints of critical paths. If any faulttolerance mechanism is provided for timing faults, it is not necessary to keep the constraints. From these observations, we propose a fault-tolerance technique for timing failures, which e ciently utilizes the speculative execution mechanism and reduces power consumption. We call the technique constructive timing violation. This paper evaluates our proposal using a cycle-by-cycle simulator and nds its e ciency on energy consumption.